AFE=0, DMAMUX3=0, LPTMR=0, FTFA=0, ADC=0, RNGA=0, DMAMUX1=0, DMAMUX0=0, SIM_LP=0, CRC=0, PIT0=0, PIT1=0, DMAMUX2=0
System Clock Gating Control Register 6
FTFA | FTFA Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
DMAMUX0 | DMA MUX0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
DMAMUX1 | DMA MUX1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
DMAMUX2 | DMA MUX2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
DMAMUX3 | DMA MUX3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
RNGA | RNGA Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
ADC | SAR ADC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PIT0 | PIT0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PIT1 | PIT1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
AFE | AFE Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
CRC | Programmable CRC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
LPTMR | LPTMR Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
SIM_LP | SIM_LP Clock Gate Control 0 (0): Clock is disabled 1 (1): Clock is enabled |
SIM_HP | SIM_HP Clock Gate Control 1 (1): Clock is always enabled to SIM |